San Francisco, CA – 11478998 Job Title RM- Application Developer- ASIC Design Verification Staff Engineer – Bay Area DescriptionComment Yes its specific to Silicon industry Testbench development – System Verilog UVM and C tests Integrationdevelopment of C testsAPIs and SW build flow Integrationdevelopment of UVM mailboxes and HWSW communication components Integration of lower level UVM testbenches Test plan development Power Aware testbench development and simulations Seamless porting… between simulationemulationprototyping platforms Regression setup and debug for RTLGate Level NetlistUPF PA simEmulationProto Coverage collection and closure Working with cross functional teams (DVArchDesignFW) to identify coverage scope Minimum Qualifications 5+ years of experience in RTL Design and Verification area of which 2+ years of experience in SoC Design Verification and HWSW verification Deep knowledge of System Verilog UVM and vertical tetsbench integration Knowledge of low level HWSW interaction and debug Knowledge…