Tachyum – Redwood Estates, CA – RTL Design Engineer Working on PCIe, DRAM and high speed bus interfaces for an SOC. Required: Logic design experience Strong understanding of processor and computer architecture Verilog or System Verilog PCIe, DRAM and other high speed interfaces Synthesis / STA (Stating timing analysis) / CDC / LINT Desired: Knowledge of programming languages C, scripting (Perl / shell / python / awk) is a plus Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants…