Austin, TX – Minimum Required Skills Verification, Verilog, Python, Shell, UVM If you are a Senior Design Verification Engineer with experience, please read on! Top Reasons to Work with Us 1. Based in Cedar Park area, we are a semiconductor company. 2. Our company has been around for over a decade, so we offer a unique balance of stability and a small, tight-knit feel. 3. You will have the chance to lead new development projects with a talented team. What You Will Be Doing – Advanced UVM based test bench… development and debugging – Defining, documenting, developing and executing RTL verification testcoverage at system level – Performance verification and power-aware verification – Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog – Help improve and refine verification process, methodology, and metrics – UVM expertise on complex SoC projects from test bench development to verification closure What You Need for this Position – 8 or more years of design and verification experience…