Cadence Design Systems – Austin, TX – At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for a design Verification expert with good subsystem and SOC level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Ability to coach and mentor less experience teammates. Should have worked on time-bounded projects leading to Si realization. Cadence is not providing work authorization sponsorship , including OPT or F1…, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. A strong positive attitude and ability to work in a team is a must. Self-motivated and willing take up additional responsibilities to contribute to teams success. Required experience – Worked on Subsystem / SOC level verification projects – Experience in ARM based designs. – In-depth knowledge SV-UVM – Expertise in architecting, design…